Table-based version

Directory /pub/cbm/schematics/computers/p500/

Commodore 500, a.k.a. PET II schematic diagrams

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[Parent directory]

drives@

Disk drives

firmware@

System firmware

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Commodore 500 µP, address & data buffers, arbitration logic

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system decode & buffer control

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VIC; video memory; video bus buffers

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SID; 192k DRAM array refresh logic

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192k DRAM address mux & control

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192k*8 DRAM array [64k standard, 128k optional]

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64k DRAM array and address mux

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system ROM/RAM array

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gameport interface; keyboard interface; RS232C interface

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interrupt prioritization; IEEE488 interface; user/game port interface

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cassette i/f port

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main oscillators & PLL

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video output circuit

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[List of power filter capacitors for each IC]

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[FPLA logic equations]

README

Information about the Commodore 500 a.k.a. PET II.

keyboard.txt

Commodore P500 Keyboard Schematic. Composed by Tony Duell <[email protected]>.

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